Job Opening:  Verification Engineer

Designations
 Verification Engineer
Job Description
 

 5-8 years experience in Chip & block level verification, using UVM/Vera/SV/NTB. Experience in DV architecture, test plan environment setup, simulation, and coverage analysis and closure for full chip or major block. Responsibilities will include development of complex self-checking test benches with constrained Random stimulus generation. Write detailed test plans, develop test cases, run simulations and debug functional errors, code coverage and functional coverage

Desired Profile
 

 Responsible for DV architecture, test plan, environment setup,Verification and code/functional coverage analysis & review

Experience
 5-8 yrs
Industry type
 
Role
 Verification Engineer
Functional Area
 Software
Education
 Any Grads or Post Grads .
Compensation
 As per norms
Location
 Chennai
Keywords
 Chip and Block Level Verification using UVM/Vera/SV/NTB
Contact
 Hariharan
Telephone
 0427-6500901
Email
 hariharan@venpastaffing.com
Job posted
 2014-02-06
Reference
 wcsveng
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